The present inventions are related to systems and methods for equalizing data, and more particularly to systems and methods for controlling an equalization process.
Storage devices generally include a read/write assembly including a write head operable to write data to a storage medium, such as tape or disk. Data that is to be written to the medium is generated by a system, such as a computer. The data comes from the computer in digital form, and is converted into analog form, prior to being sent to the write head. Physical phenomena can adversely affect the analog signal at the head. For example, when the digital data is constant (e.g., a steady stream of high or low voltage levels), time domain drift can occur.
Equalization is a way to prevent drift. Equalization compensates for analog effects that interfere with the signal at the write head by changing the time domain pulse widths and introducing toggling into the data stream. For example, a single bit of logical value ‘one’ may be replaced with 4 equalization bits, where three of the bits are a logical ‘one’ and the fourth bit is a logical ‘zero’. In conventional systems where equalization is used, the equalization process is usually integrated close to, or even within, the processor (e.g., the storage device control processor) that is generating the digital data. This arrangement renders conventional approaches to equalization quite limited in the flexibility and extent to which equalization can be applied.
FIG. 1 illustrates a simplified prior art storage system architecture 100 that employs equalization. The system of FIG. 1 includes a controller chip 102 and a preconditioning chip 104. The controller chip 102 includes a processor unit 106 and an equalization unit 108. The preconditioning chip 104 includes a digital to analog (D/A) converter 110 and an analog preparation unit 112. The processing unit 106 provides data to the equalization unit 108, which equalizes the data and sends the equalized data to the preconditioning chip 104, which converts the data to analog and prepares the data for delivery to the write head 114. The write head 114 then writes the data to storage media (not shown).
In the architecture of FIG. 1, the preconditioning chip 104 is in close proximity to the write head 114 to accommodate the requisite high data rates (e.g., 600 MHz-1 GHz) for writing data. In some cases, the preconditioning chip 104 is integrated with the write head 114. The preconditioning chip 104 and write head 114 are formed of a semiconductor material, such as Silicon Germanium (SiGe), which is able to handle the higher data rates. By contrast, the controller chip 102 is relatively far from the write head 114 and, to reduce costs, is generally formed of a semiconductor material, such as complementary metal-oxide-semiconductor (CMOS) Silicon, which does not need to operate at the higher data rates employed by the write head.
The distance of the controller unit 102 from the preconditioning chip 104, and the lower speed material of the controller unit 102, gives rise to limitations with respect to equalization. A specific limitation is the maximum data rate that can be used to transmit data from the controller chip 102 to the preconditioning chip 104. The degree of equalization is limited by the system clock (e.g., 200 MHz) of the controller chip 102. In addition, the distance between the controller chip 102 and the preconditioning chip 104 limits the rate at which data can be transmitted therebetween with a sufficiently low bit error rate. As a result, the degree of equalization is fairly limited in the conventional architecture.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for providing equalization of data.